In many data communication arrangements, no separate clock signals are transmitted. This requires recovering the clock at the receiving end in order to then recover the data. This can be characterized as the problem, in digital communications, of transferring digital signals between multiple clock timing domains. Multiple clock timing domains include the clock timing domain of a transmitting device as well as the clock timing domain of a receiving device. It is not unusual to transmit digital signals between clock timing domains having nearly the same underlying frequency clock, but different or varying phases with respect to each other.
In the prior art, clock recovery circuits provide clock recovery from serial data streams in devices called tracking receivers. Various tracking architectures have been used for this purpose. For example, phase locked loop (PLL) based and delay locked loop (DLL) based tracking architectures have been used. These circuits have various disadvantages. A PLL is an oscillator and injects noise into the surrounding substrate/system. Furthermore, a PLL uses a voltage level to control its oscillation frequency. Hence it is prone to frequency distortions introduced through very low levels of noise on the control lines. A PLL also requires an analog loop filter to damp input noise from interfering with the tracking of the remote transmit clock. This loop filter is an RC time constant network consisting of polysilicon blocks for resistance and gates for capacitance. The analog loop filter consumes a substantial amount of on-die area.
Classic DLL based tracking architectures also present problems. These also are prone to frequency distortion introduced through low levels of noise and utilize analog filters which consume a large on-die area. In addition, a DLL has a finite delay range. A DLL tracks the remote transmit clock by taking a local clock and delaying it until it matches the phase of the remote clock. If the remote clock skews over time or temperature the DLL tracking this clock must add or subtract delay to its local version. If the DLL is asked to delay less than zero, it must add a bit time to that delay to remain within its functional range. Complex circuitry must ignore the additional bit that the adjustment action of the DLL inserts into the recovered data stream. This circuitry must also insert a bit into the recovered data stream when the DLL is asked to delay more than its fixed range.
An approach to digital phase interpolation which overcomes some of these disadvantages is disclosed in Digital Systems Engineering, 1998, by Dally and Poulton, p. 604-605. The interpolator is described as similar to a typical delay stage but has two differential pairs. In a digitally controlled embodiment, a plurality of digitally controlled tails on each of the differential pairs are provided to select different phases, between two import phases. This avoids some of the problems noted above with PLL and DLL architectures. However, this approach has its own problems. For example, this circuit could require a multiplexer circuit for selecting source clocks. This adds undue additional circuitry and clock distortion during switching. The textbook interpolator also requires a (noise prone) voltage bias to keep the tail current transistors saturated. Furthermore, common mode noise due to charge injection at the nodes between the tail and switching transistors is a problem which is described, but not solved, in the textbook version, when using equally weighted current sources.
A need, therefore, exists for a phase interpolator which avoids the problems found in these various prior art architectures.